1. Field of the Invention
This invention is related to the field of interrupts in computer systems and, more particularly, to handling edge-triggered and level-sensitive interrupts.
2. Description of the Related Art
Computing systems generally include one or more processors that serve as central processing units (CPUs), along with one or more peripherals that implement various hardware functions. The CPUs execute the control software (e.g. an operating system) that controls operation of the various peripherals. The CPUs can also execute applications, which provide user functionality in the system. Additionally, the CPUs can execute software that interacts with the peripherals and performs various services on the peripheral's behalf.
The peripherals can cause the CPUs to execute software on their behalf using interrupts. Generally, the peripherals issue an interrupt to the CPU, typically by asserting an interrupt signal to an interrupt controller that controls the interrupts going to the CPU. The interrupt causes the CPU to stop executing its current software task, saving state for the task so that it can be resumed later. The CPU can load state related to the interrupt, and begin execution of an interrupt service routine. The interrupt service routine can be driver code for the peripheral, or may transfer execution to the driver code as needed. Generally, driver code is code provided for a peripheral device to be executed by the CPU, to control and/or configure the peripheral device.
Interrupts can be defined to be either edge-triggered or level-sensitive. An edge-triggered interrupt signals an interrupt via the assertion of the interrupt signal. The occurrence of the rising edge (or falling edge, for active low interrupt signals) is the request for interrupt. The level on the edge-triggered interrupt signal has no particular meaning, and the interrupt signal need not remain asserted to continue the request for interrupt. On the other hand, a level-sensitive interrupt indicates a request for interrupt via the level of the signal. Thus, the level-sensitive interrupt signal is asserted (e.g. high, for an active-high interrupt signal, or low, for an active-low interrupt signal) and the asserted level indicates that request. The request remains active until the deassertion of the level-sensitive interrupt signal (e.g. low, for an active-high interrupt signal, or high, for an active-low interrupt signal). Deassertion of the level-sensitive interrupt signal indicates that no interrupt is requested. In some cases, deassertion can happen even if the interrupt has not yet been serviced.
In a system that includes both edge-triggered and level-sensitive interrupts, communicating the interrupts through the system and managing the interrupts correctly can be a challenge.